1. Field of the Invention
The present invention relates to a semiconductor memory device and in particular to a refreshing technique in a semiconductor memory device.
2. Description of the Related Art
There has been much progress recently in increasing the memory capacity and miniaturization in semiconductor memory devices such as DRAM. Thus, the number of memory cells to be refreshed is also increasing with the increase in the memory capacity. The refreshing operation is carried out in response to a refresh command, and a time period between the refresh commands is defined by tRFC (hereinafter, referred to as “refresh command time”). When the memory capacity is increased while keeping the refresh command time tRFC to constant, the number of memory cells to be refreshed per unit time increases, resulting in increase in peak current consumption. For this reason, the specification of DRAM have been standardized in such a manner that the refresh command time tRFC is relaxed to reduce the number of memory cells to be refreshed per unit time and to suppress the increase in current consumption, with increase in the memory capacity.
In the generation of 1 G bit-DDR-I/II, mobile terminals and products on which a large capacity memory system is mounted occupy a more important position in the DRAM market. Accordingly, the technique for further reducing the current consumption becomes more important in such a product.
Next, a conventional refreshing operation will be described. FIGS. 2A to 2D are diagrams showing a memory cell region of a conventional semiconductor memory device to which a refreshing operation is carried out. In the conventional semiconductor memory device, the memory cell region has eight banks (BANKs 0 to 7), and each bank has four blocks. A Y decoder YDEC for bit line selection is arranged between the right block and the left block in the bank. A sub amplifier and an X decoder XDEC for word line selection are arranged between the upper block and the lower block in the bank. Each block has 8×24 memory sub arrays ARY. Two memory sub arrays ARY adjacent in the left and right direction shares a sense amplifier AMP and an equalizer EQ through a switching circuit having shared MOS transistors.
When a clock enable signal CKE, a chip select signal /CS, a row address strobe signal /RAS, a column address strobe signal /CAS, and a write enable signal /WE are inputted, the semiconductor memory device recognizes a combination of these signals as an external refresh command REF and carries out a refreshing operation.
The refresh period of the external refresh command REF is a period from T1 to Tn shown in FIG. 1A. Referring to FIGS. 1B to 1E, a refreshing operation to objective banks is carried out in response to the external refresh commands REF. First, as shown in FIG. 2A, the refreshing operation is carried out to BANKs 0 and 4 as the objective banks at timing T1. At this time, the refreshing operation is carried out on 16 memory sub arrays in the blocks adjacent in an upper and down direction in the objective banks, as shown on the right side of FIG. 2A. Subsequently, as shown in FIG. 2B, the refreshing operation is carried out to BANKs 1 and 5 as the objective banks at timing t3. At this time, the refreshing operation is carried out on 16 memory sub arrays in the blocks adjacent in an upper and down direction in the objective banks, as shown on the right side of FIG. 2B. Subsequently, as shown in FIG. 2C, the refreshing operation is carried out to BANKs 2 and 6 as the objective banks at timing T5. At this time, the refreshing operation is carried out on 16 memory sub arrays in the blocks adjacent in an upper and down direction in the objective banks, as shown on the right side of FIG. 2C. Also, the refreshing operation of the BANKs 0 and 4 is completed. Subsequently, as shown in FIG. 2D, the refreshing operation is carried out to BANKs 3 and 7 as the objective banks at timing T7. At this time, the refreshing operation is carried out on 16 memory sub arrays in the blocks adjacent in an upper and down direction in the objective banks, as shown on the right side of FIG. 2D. Also, the refreshing operation of the BANKs 1 and 5 is completed. At timing Tn, the refreshing operation to BANKs 3 and 7 is completed. In this way, in the conventional semiconductor memory device, the refreshing operation is carried out in a time divisional manner, in order to reduce consumption current. The number of memory sub arrays to be refreshed at the same time is 64 (=16×4).
Next, the refreshing operation to each bank will be described below in detail. FIGS. 3B to 3F corresponds to the refreshing operation of the BANKs 0 and 4, FIGS. 3G to 3K corresponds to the refreshing operation of the BANKs 1 and 5, FIGS. 3L to 30 corresponds to the refreshing operation of the BANKs 2 and 6, and FIGS. 3P to 3T corresponds to the refreshing operation of the BANKs 3 and 7. Since all the refreshing operations are identical except the refresh start timing, only the refreshing operation to the BANKs 0 and 4 shown in FIGS. 3B to 3F will be described.
First, the potentials of a connection control signal SHR1T and an equalizer control signal BLEQT are changed from a potential VPP to a potential VSS, to turn off the two shared MOS transistors and an equalizing circuit EQ for equalizing the potentials of bit lines in an inactivated sub memory array (sub memory array containing no memory cells to be refreshed) side of the BANK. At this time, because the two shared MOS transistors in the activated sub memory side are turned on, a connection control signal SHR0T continues to have the potential VPP. Next, a word line selection signal MWLB <0> and a sub word line selection signal FXB <0> are selected by the X decoder, and the potentials thereof are changed from the potential VPP to the potential VSS. As a result, the potential of a word line SWLT <0> is changed from the potential VSS to the potential VPP. In this way, when data from one of the memory cells MC is read out on bit lines BL0T/B, the potential of a sense amplifier control signal SAET is changed from the potential VSS to the potential VCL, to start to amplify the data on the bit lines. After the data on the bit line is amplified sufficiently and rewritten into the memory cell, the potential of a sense amplifier control signal SAET is changed from the potential VCL to the potential VSS, to complete the amplifying operation. Subsequently, the potentials of the equalizer control signal BLEQT and the sub word line selection signal FXB <0> are changed from the potential VSS to the potential VPP, to complete the rewriting operation into the memory cells. Thus, the first refreshing operation is completed. The other BANKs are refreshed in a time divisional manner and the refreshing operations thereof are started one after another. The operations are the same as that described above, and the description is omitted.
As described above, for reduction of current consumption, the circuit has been designed so that the memory sub arrays are refreshed in the time divisional manner to reduce the peak current consumption. However, the method cannot reduce the average current consumption.
In conjunction with the above description, a semiconductor memory device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 5-314766). The semiconductor memory device in this conventional example includes a shared sense amplifier which is connected with two pairs of bit lines and a switching transistor interposed in each of the bit lines of the two pairs. The shared sense amplifier is connected to one of the two pairs of bit lines by switching of the switching transistor. Memory cells on two word lines which cross the connected pair of bit lines are refreshed continuously in units of word lines one after another in a /CAS before /RAS refresh mode and a self refresh mode. During this operation, the signal level of a bit line selection signal supplied to the gate of the switching transistor corresponding to the connected pair of bit lines is kept constant. Also, a semiconductor memory device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 9-63266). The semiconductor memory device in this conventional example has a normal operation mode and a self refresh mode with an operation speed slower than that the normal operation mode. In the semiconductor memory device in this conventional example, a sense amplifier is connected with first and second sense nodes, and amplifies a potential difference generated between the first and second sense nodes. A first bit line pair is arranged on one side of the sense amplifier, and a second bit line pair is arranged on the other side of the sense amplifier. A plurality of the word lines cross the first and second bit line pairs. A row decoder selectively activates one of the word lines based on a row address signal. First switches are connected between the first and second sense nodes and the bit lines of the first pair, and second switches are connected between the first and second sense nodes and the bit lines of the second pair. A control unit controls the first and the second switches so that one current of the first and second bit line pairs is connected to the sense amplifier in the normal operation mode, and so that one of the first and the second bit line pairs is connected to the sense amplifier, the connected bit line pair connected is disconnected from the sense amplifier after data is read out on the bit lines of the connected pair, and then the disconnected pair of bit lines is reconnected to the sense amplifier after the sense amplifier is activated, in the self refresh mode. The power consumption in the self refresh mode is reduced in the conventional semiconductor memory device.
Also, a semiconductor memory device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 10-222977). The semiconductor memory device in this conventional example has a plurality of memory blocks and a gate circuit connected between each of the memory blocks and one of the shared bit line sense amplifiers. A refresh row active signal that is activated in a certain interval is generated, and a plurality of block selection signals are generated to be selectively activated when the refresh row active signal is active. A latch switching control signal is generated, which is set by each of corresponding block selection signals and is reset by a block selection signal corresponding to the memory block to be next refreshed. When the latch switching control signal is active, the corresponding gate circuit is turned on and another gate circuit connected to the same bit line sense amplifier is turned off. During a block refresh cycle, the turn-on state or turn-off state of the gate circuit is kept constant. In this manner, the power consumption is reduced.
Also, a dynamic semiconductor memory device is disclosed in Japanese Laid Open Patent Application (JP-P2000-353383A). The dynamic semiconductor memory device in this conventional example includes a plurality of banks composed of a plurality of sub arrays. A sense amplifier circuit is shared by the different sub arrays in the banks. The memory cell array has the plurality of banks and the sense amplifier circuits. The dynamic semiconductor memory device in this conventional example has a row access mode for activating selected sub arrays in each bank for reading or writing data, and a refresh mode for activating a plurality of sub arrays in each bank at the same time and refreshing the memory cell data. In a control circuit, the number of sub arrays activated a same timing in the bank in the refresh mode is greater than the number of the sub arrays activated in the bank in the row access mode. According to the conventional dynamic semiconductor memory device, the probability of operational restriction is reduced to enable high-speed operation and DRAM of a non-independent bank type is provided.